Drum "synthesis", Resonator, Tape delay, Phaser, Knob recorder, Quantizer, Pitch/Envelope tracker, LFO/VCO, Waveshaper, S&H, Slew limiter, LP/HP filter.
The Disting is a multifunction module, offering a variety of CV and audio processes, including a selection of oscillators (LFOs/VCOs). All algorithms have two high-precision inputs and outputs, and a third control input, exposed on a front panel knob and a CV input.
The algorithms are:
• Precision Adder with integer voltage offsets
• Linear/Exponential Converter
• Sample and Hold with noise source and
adjustable slew rate
• LFO with through zero frequency control
• Four Quadrant Multiplier with integer multiply/divide
• Quantizer with selectable scales
• Slew Rate Limiter with linear and
• Clockable LFO with multiply/divide
• Full-wave Rectifier
• Comparator with adjustable hysteresis
• Pitch and Envelope Tracker
• VCO with linear FM sine and saw outputs
• Dual Waveshaper wavefolder and
• Clockable Delay/Echo
•VCO with waveshaping saw/triangle
and pulse outputs
MK III adds:
• Drum synthesis
• Tape delay
• Knob recorder
• LP/HP filter
• VC delay line
• Tap tempo
The Disting's specifications are as follows:
• Panel width: 4HP
• Module depth: 53mm
• X & Y inputs, A & B outputs
• Sample rate: 78.125kHz
• ADC: 24 bit, THD+N -93dB, Dynamic range 99dB, SNR 99dB
• DAC: 24 bit, THD+N -94dB, Dynamic range 105dB, SNR 104dB
• Z input sample rate: 10kHz approx
• CPU: Microchip PIC32MX at up to 40MHz
• Current draw: 111mA on the +12V rail, 37mA on the -12V rail (148mA total)
The front panel is drilled for both Doepfer and Analogue Systems mounting holes (using a 'slot' rather than a single round hole). The power connector is a Doepfer standard 10 way IDC, with -12V furthest from the top of the board.
The Disting is based around a PIC microcontroller, with a programming/debug header available on the board. Using Microchip's free development tools a user can easily hack the Disting to perform their own functions.
It is our intention to provide an open source code framework into which developers can slot their own algorithms.
In the mark II, the MCU has been upgraded to one with more memory, wich means that the "clocked delay" mode's maximum delay time is now over twice as large, about